<= Assignment Operator In Verilog
Answer : "<=" in Verilog is called non-blocking assignment which brings a whole lot of difference than "=" which is called as blocking assignment because of scheduling events in any vendor based simulators. It is Recommended to use non-blocking assignment for sequential logic and blocking assignment for combinational logic, only then it infers correct hardware logic during synthesis. Non-blocking statements in sequential block will infer flip flop in actual hardware. Always remember do not mix blocking and non-blocking in any sequential or combinational block. During scheduling process of simulator: There are four regions and order of execution of commands as follows 1) Active region --Blocking assignments --Evaluation of RHS of non-blocking assignments(NBA) --Continuous assignment --$display command --Evaluate input and output of primitives 2) Inactive region --#0 blocking assignments 3) NBA(non-blocking assignment up...