ASM X86_64 AVX: Xmm And Ymm Registers Differences
Answer : xmm0 is the low half of ymm0 , exactly like eax is the low half of rax . Writing to xmm0 (with a VEX-coded instruction, not legacy SSE) zeros the upper lane of ymm0 , just like writing to eax zeros the upper half of rax to avoid false dependencies. Lack of zeroing the upper bytes for legacy SSE instructions is why there's a penalty for mixing AVX and legacy SSE instructions. Most AVX instructions are available with either 128-bit or 256-bit size. e.g. vaddps xmm0, xmm1, xmm2 or vaddps ymm0, ymm1, ymm2 . (The 256-bit versions of most integer instructions are only available in AVX2, with AVX only providing the 128-bit version. There are a couple exceptions, like vptest ymm, ymm in AVX1. And vmovdqu if you count that as an "integer" instruction). Scalar instructions like vmovd , vcvtss2si , and vcvtsi2ss are only available with XMM registers. Reading a YMM register is not logically different from reading an XMM register, but writing the low ...